Search - verilog fir

[VHDL-FPGA-Verilog] fir_filter

Description: 一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
Platform: | Size: 1024 | Author: ningbo | Hits:

[VHDL-FPGA-Verilog] LPF

Description: 数字低通FIR滤波器Verilog实现代码-Verilog digital FIR filter implementation code
Platform: | Size: 4096 | Author: 程超 | Hits:

[VHDL-FPGA-Verilog] firlms

Description: 基于FPGA的自适应FIR滤波器的verilog设计与实现-Adaptive FIR Filter Based FPGA Design and Implementation of verilog
Platform: | Size: 1024 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] fir_filter_generator

Description: FIR有限冲击响应滤波器verilog代码和测试-FIR finite FIR filter verilog code and test
Platform: | Size: 1845248 | Author: 李雪利 | Hits:

[assembly language] 8_oeder_signed_parellel_DA_FIR

Description: 本程序使用Verilog编写的程序。本例是1个8阶对称系数的FIR滤波器，采用并行分布式算法。输入位宽为12位，输入是有符号的，即有正有负。-it s a program with Verilog
Platform: | Size: 2048 | Author: 张树林 | Hits:

[VHDL-FPGA-Verilog] firfilt

Description: FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
Platform: | Size: 5120 | Author: mmmm1111111111 | Hits:

[Graph program] filter_dds_10.29_7.2

Description: 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
Platform: | Size: 1033216 | Author: chen | Hits:

[Windows Develop] TverilogFIRh

Description: 基于verilog的FIR滤波器程序设计（调试过的的）-verilog ， -Verilog program of FIR filter design (debug)-Verilog,
Platform: | Size: 645120 | Author: 表现 | Hits:

[VHDL-FPGA-Verilog] HalfbandDec

Description: 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
Platform: | Size: 1024 | Author: 小梦 | Hits:

[VHDL-FPGA-Verilog] rc_flt

Description: 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validation, using verilog language.
Platform: | Size: 4096 | Author: 小梦 | Hits:

[Other] FIR_lowpass

Description: FIR 滤波器 verilog 语言编写很实用-FIR filter design
Platform: | Size: 1024 | Author: 小关 | Hits:

[Other] da_fir

Description: 基于verilog的分布式算法FIR滤波器有两个文件一个用来生成查找表-FIR filter using Distributed Algorithm.
Platform: | Size: 2048 | Author: 小关 | Hits:

[VHDL-FPGA-Verilog] my_fir

Description: Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
Platform: | Size: 1024 | Author: 韩帅 | Hits:

[VHDL-FPGA-Verilog] FIR_Lowpass

Description: 用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
Platform: | Size: 796672 | Author: 李桐 | Hits:

[Other] filter

Description: verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
Platform: | Size: 2211840 | Author: kimchiman | Hits:

[Other] da_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码（本人小论文代码，通过验证）本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能，采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA)，将MAC运算转化为查找表(Look-Up-Table, LUT)输出，不仅能在硬件规模上得到改善，而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器，并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[VHDL-FPGA-Verilog] filter_signed_and_unsigned

Description: FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
Platform: | Size: 3072 | Author: 范慧敏 | Hits:

[Other] proiect

Description: Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
Platform: | Size: 1844224 | Author: valentina199114 | Hits:

[VHDL-FPGA-Verilog] fir_filter_50Mhz

Description: 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
Platform: | Size: 8773632 | Author: Eason | Hits:

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[VHDL-FPGA-Verilog] fir_filter

[VHDL-FPGA-Verilog] LPF

[VHDL-FPGA-Verilog] firlms

[VHDL-FPGA-Verilog] robust_fir_latest.tar

[VHDL-FPGA-Verilog] fir_filter_generator

[assembly language] 8_oeder_signed_parellel_DA_FIR

[VHDL-FPGA-Verilog] firfilt

[Graph program] filter_dds_10.29_7.2

[Windows Develop] TverilogFIRh

[VHDL-FPGA-Verilog] HalfbandDec

[VHDL-FPGA-Verilog] rc_flt

[Other] FIR_lowpass

[Other] da_fir

[VHDL-FPGA-Verilog] my_fir

[VHDL-FPGA-Verilog] FIR_Lowpass

[Other] filter

[Other] da_fir

[VHDL-FPGA-Verilog] filter_signed_and_unsigned

[Other] proiect

[VHDL-FPGA-Verilog] fir_filter_50Mhz

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